In traditional embedded multiprocessor systems, the interconnection between processors is achieved through a time-sharing shared bus, where all communication contends for bus bandwidth, thereby resulting in more processors, available bandwidth per processor. The less, the serious bottleneck of system information transmission capacity. And the bus has a large number of pins, which brings certain electrical and mechanical characteristics, so that the signal frequency and the signal transmission distance are greatly restricted.
RapidIO bus technology is an interconnect technology based on high-performance packet switching with extremely low latency (nanoseconds) and high bandwidth. The proposed RapidIO bus technology eliminates the bandwidth bottleneck problem and successfully solves the interconnection problem between the processor integrated chips and the circuit board. At present, RapidIO has become the only intra-system serial interconnect protocol standard. The world's major semiconductor companies have successively launched related products based on RapidIO technology. The system based on RapidIO communication architecture technology has been widely used in telecommunications, defense, medical and other industries. use.
Currently in a high-speed embedded multiprocessor system, it is generally composed of processors such as PPC, DSP, and FPGA. This paper tests and verifies the design of the RapidIO node of the FPGA.
2 RapidIO Technology Overview
RapidIO provides more than 10 Gbps of bandwidth (the RapidIO 2.0 specification provides 100 Gbps of bandwidth), and all of its protocols are implemented in hardware, independent of software. Suitable for high-speed data transmission between chips and chips, boards and boards, systems and systems.
The RapidIO protocol uses a three-tier hierarchical architecture. The logical layer specification is at the highest level, defining the full protocol and packet format, which provides the necessary information for the endpoint device to initiate and complete transactions. The transport layer specification is in the middle layer and defines the RapidIO address space and the routing information needed to transport packets between endpoint devices. The physical layer specification is at the bottom of the entire hierarchy, including details of device-level interfaces such as packet transfer mechanisms, flow control, electrical characteristics, and low-level error management.
RapidIO's transport operations are based on request and response mechanisms, and transport operations can interpolate control symbols intermittently during packet transmission. A packet (PACKET) is a communication unit of an endpoint device in a system. A transfer request is generated by the initiator (inTIator), and the request packet is transmitted to the adjacent switching device, thereby entering the switching mechanism, and the complete request packet is transmitted to the target device through the switching mechanism, and the target device completes the corresponding request according to the request. After the operation, the corresponding response packet is sent and transmitted back to the initiator through the switching mechanism, at which time a complete transmission process is completed. Control symbols are typically used for transport management in physical layer interconnects, such as packet acknowledgment, flow control information, and maintenance functions. As shown in Figure 1.
Figure 1 RapidIO transmission operation
RapidIO's three-tier architecture interconnects different units, and different units communicate in packets. Such an interconnection network can have a very flexible system topology, and a switching-based interconnection system is commonly used. The transfer of a packet from one processing unit to another is performed by the switching unit, which obtains which processing unit the packet is to arrive by decoding the transmission field in the packet format. Since usually one request packet corresponds to one response packet, the transport field in the packet format also defines the return path of the response packet.
3 RapidIO FPGA node implementation
A typical system network consists of three nodes: PPC, DSP, and FPGA. As the performance of processors such as CPUs, DSPs, and FPGAs is greatly improved, improving the bus performance of connecting these high-performance devices is the key to improving system performance. RapidIO technology has been implemented in some processors, system logic, FPGAs and ASICs. For example, Xilinx has sold RapidIO's terminal interface logic IP core; TI's DSP chip TMS320C6455 integrates serial RapidIO peripherals; Motorola has already The RapidIO interface logic is integrated into the PowerQUICC III processor; Tundra offers the 8-port serial 1x/4x RapidIO switch chip Tsi568A and RapidIO bridge chip. Here we discuss the implementation of the RapidIO node in the FPGA.
The RapidIO node on the FPGA in the RapidIO network can be implemented using the Xilinx RapidIO solution. The Xilinx RapidIO solution is shown in Figure 2. It consists of four parts: the physical layer core, the logical transport layer core, the buffer core, and the reference design. The reference design controls access to the clock, reset, and configuration space.
Figure 2 Serial RapidIO Functional Block Diagram
The logical layer and transport layer interface are shown in Figure 3. The logical layer is connected to the physical layer through a Xilinx-specific local Link interface to form a RapidIO node. The logic layer is divided into several modules to control the concatenation and parsing of the sending and receiving packets. The user interface (User InteRFace) includes four ports (IniTIator Request, IniTIator Response, Target Request, and Target Response), from which the packet is sent to the remote node or the packet sent by the remote node is received. It is the user communication when using the Xilinx SRIO solution. The interface used. It is also possible to initiate read and write operations to the local configuration registers from these ports. Maintenance interface contains
Two ports (Maintenance Request/Response Port and Configuration Register Port) control the reading and writing of the logic layer configuration registers and user-defined registers or physical layer configuration registers.
Figure 3 logical layer and transport layer interface
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